Sigma-delta data converters have enjoyed popularity because they rely on precise timing rather than precisely-matched components, and are thus easy to manufacture in integrated circuit form. The sigma-delta technique is commonly used for both analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A first-order sigma-delta modulator for an ADC subtracts a feedback signal from a received analog input signal to provide an error signal. The error signal is integrated, and the integrated error signal is input to a quantizer. The quantizer resolves the integrated error signal into one of a finite number of states to provide the output of the sigma-delta modulator portion of the ADC. This modulator output is provided to an input of a feedback DAC, the output of which provides the feedback signal. The digital output of the quantizer has a density proportional to the analog level of the signal. However, a decimator is required to construct the digital output code from the output and to attenuate the quantization noise that the sigma-delta modulator enhances in the stopband.
One-bit quantizers are commonly used, making the output of the sigma-delta modulator a single-bit stream. However, multi-bit quantizers are sometimes used. A second-order sigma-delta modulator is also commonly used in place of the first-order modulator. The second-order modulator differs from the first-order modulator by including two integration and feedback correction stages prior to the quantizer.
The decimator must integrate the output of the quantizer to produce a multi-bit digital data stream at a lower clock rate. For example, a single-bit modulator may provide a digital pulse stream at 10 megahertz (MHz), but the ADC may decimate the digital output code by a factor of 128:1 to provide an output sample stream at approximately 80 kilohertz (kHz). A known rule of thumb in sigma-delta ADC design is for the integrator to have one more stage than the order of the modulator. For example, a three-stage integrator is desirable for a second-order modulator to attain good attenuation in the stopband.
Practical problems arise in implementing a sigma-delta ADC in integrated circuit form. In known integrated circuit ADCs the digital integrator, rather than the modulator, consumes the majority of circuit area. This relationship is caused by the way the digital integrator is implemented. Each integrator stage adds a digital input signal to a previous (delayed) sum to provide a current sum. To implement the addition function, known integrator stages include at a minimum a number of full adders equal to the bit length of the output of the particular stage, and may require more depending on the type of adder used. Each full adder requires many logic gates in order to implement the logic equations. By contrast, the delay function requires only one flip-flop per bit, and the modulator itself may be implemented with one DAC and only a small amount of analog circuitry. A reduction in the size of the digital integrator would thus have a large effect on the reduction of the overall size cost of the ADC.